Next-generation analog computing chipsets for artificial intelligence (AI) applications could be completely faster and consume less power, thanks to a design framework developed by researchers at the Indian Institute of Science (IISc).
Using their new design framework, the team has built a prototype of an analog chipset called ARYABHAT-1 (Analog Reconfigurable Technology and Bias-Scalable Hardware for AI Tasks). This type of chipset could be especially helpful for artificial intelligence (AI)-based applications such as object or speech recognition – think Alexa or Siri — or those that require massively parallel computing operations at high speeds, noted in an IISc statement.
Most electronic devices, especially those involving computing, use digital chips because the design process is simple and scalable. “But the advantage of analog is huge. You’ll get orders of magnitude improvement in power and size,” explains Chetan Singh. ThakurAssistant Professor in the Department of Electronic Systems Engineering (DESE), IISc, whose laboratory is leading efforts to develop analog chipsets. In applications that do not require precise calculations, analog computing has the potential to outperform digital computing because the former is more energy-efficient.
However, there are many technical hurdles to overcome when designing analog chips. Unlike digital chips, testing and co-designing analog processors is difficult. Large-scale digital processors can be easily synthesized by compiling high-level code, and the same design can be ported to different generations of technology development – eg, from 7 nm chipsets to 3 nm chipsets – with minimal modifications. with. Because analog chips do not scale easily – they need to be individually optimized when transitioning to next generation technology or new applications – their design is costly.
Another challenge is that when it comes to analog design it’s not easy to trade off precision and speed with power and area. In digital design, simply adding more components such as logic units to a single chip can increase accuracy, and the power at which they operate can be adjusted without affecting device performance.
To address these challenges, the team designed a new framework that allows the development of analog processors that scale much like digital processors. Their chipsets can be reconfigured and programmed so that the same analog module can be ported over different generations of process designs and in different applications. “You can synthesize the same kind of chip at 180 nm or 7 nm as in digital design,” says Thakur.
Various machine learning architectures can be programmed Aryabhata, and like digital processors, can operate reliably over a wide range of temperatures, the researchers say. They say the architecture is also “bias-scalable” – its performance remains the same when operating conditions such as voltage or current are modified. This means that the same chipset can be configured for ultra-energy-efficient Internet of Things (IoT) applications or high-speed tasks such as object detection.
The design framework was developed as part of the PhD work of IISc student Prateek Kumar and in collaboration with Shantanu ChakrabortyProfessor at the McKelvey School of Engineering, University of Washington in St. Louis (Vashu), US, who also serves as ambassador to the McDonnell Academy of Washoe at IISc.
“It is good to see the principle of analog bias-scalable computing being manifested in reality and for practical applications,” says Chakraborty, who previously proposed bias-scalable analog circuits.
The researchers outlined their findings in two pre-print studies that are currently under peer review. They have also filed patents and plan to work with industry partners to commercialize the technology.
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